# do Compteur_8_Chiffres_Verilog.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 14:20:05 on Apr 03,2019
# vlog -work work Compteur_8_Chiffres_Verilog.vo 
# -- Compiling module Compteur_8_Chiffres_Verilog
# -- Compiling module hard_block
# 
# Top level modules:
# 	Compteur_8_Chiffres_Verilog
# End time: 14:20:05 on Apr 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 14:20:05 on Apr 03,2019
# vlog -work work Waveform1.vwf.vt 
# -- Compiling module Compteur_8_Chiffres_Verilog_vlg_vec_tst
# 
# Top level modules:
# 	Compteur_8_Chiffres_Verilog_vlg_vec_tst
# End time: 14:20:05 on Apr 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Compteur_8_Chiffres_Verilog_vlg_vec_tst 
# Start time: 14:20:05 on Apr 03,2019
# Loading work.Compteur_8_Chiffres_Verilog_vlg_vec_tst
# Loading work.Compteur_8_Chiffres_Verilog
# Loading work.hard_block
# Loading cycloneive_ver.cycloneive_io_obuf
# Loading cycloneive_ver.cycloneive_io_ibuf
# Loading cycloneive_ver.cycloneive_clkctrl
# Loading cycloneive_ver.cycloneive_mux41
# Loading cycloneive_ver.cycloneive_ena_reg
# Loading altera_ver.dffeas
# Loading cycloneive_ver.cycloneive_lcell_comb
# SDF 10.5b Compiler 2016.10 Oct  5 2016
# Loading instances from Compteur_8_Chiffres_Verilog_v.sdo
# Loading altera_ver.PRIM_GDFF_LOW
# Loading timing data from Compteur_8_Chiffres_Verilog_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /Compteur_8_Chiffres_Verilog_vlg_vec_tst File: Waveform1.vwf.vt
# after#26
# ** Warning: (vsim-3116) Problem reading symbols from linux-gate.so.1 : can not open ELF file.
# ** Note: $finish    : Waveform1.vwf.vt(56)
#    Time: 1 us  Iteration: 0  Instance: /Compteur_8_Chiffres_Verilog_vlg_vec_tst
# End time: 14:20:05 on Apr 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
